1. Field of the Invention
The present invention relates to a sampling frequency conversion apparatus having sampling frequency conversion circuits for a plurality of channels and a signal switching apparatus having a sampling frequency conversion circuit provided for each channel. More particularly, the present invention relates to a sampling frequency conversion apparatus and a signal switching apparatus suitable for inputting multi-channel signals of various numbers of channels.
2. Description of the Related Art
There has been developed a sampling frequency conversion apparatus (or, sample rate converter) which performs sampling frequency conversion processing on multi-channel digital audio signals.
FIG. 1 is a diagram showing one configuration example of such a sample rate converter (here, a later-described Matched-Phase mode is not applied). The sample rate converter performs sampling frequency conversion on AES/EBU formatted digital audio signals (hereinafter, referred to as “AES signals”), and includes AES input processing circuits 1-1, 1-2, 1-3; SRCs (sample rate converter IC) 2-1, 2-2, 2-3; and AES output processing circuits 3-1, 3-2, 3-3, corresponding to inputted AES signals (AESI1, AESI2, AESI3) for respective channels (hereinafter, these circuits for respective channels are generically described as “AES input processing circuit 1”, “SRC 2”, “AES output processing circuit 3”, and the like).
The AES input processing circuit 1 includes the following circuit blocks (1) to (3):
(1) A circuit which samples clock signals based on waveforms of inputted AES signals
(2) A circuit which demodulates audio data from inputted AES signals
(3) A circuit which samples ancillary data such as audio channel status bits from inputted AES signals
Demodulated audio data S1 and sampled clock signals S2 (SCLK_I, LRCLK_I) are supplied from the AES input processing circuit 1 to the SRC 2. Likewise, sampled ancillary data S5 are supplied from the AES input signal processing circuit 1 to the AES output processing circuit 3. FIG. 2 is a diagram showing waveforms of the clock signals SCLK_I and LRCLK_I with audio data (left channel audio data and right channel audio data) of the AES signals for one frame (1/fs period).
As shown in FIG. 1, the SRC 2 performs sampling frequency conversion on the audio data S1 using the clock signals S2 (SCLK_I, LRCLK_I) and internal sampling frequency conversion reference clock signals S4 (SCLK_O, LRCLK_O) of the apparatus. Audio data S3 on which sampling frequency conversion is performed using the SRC 2 are supplied to the AES output processing circuit 3.
The AES output processing circuit 3 converts the audio data S3 and the ancillary data S5 into original AES signals, and outputs the AES signals (AESO1, AESO2, AESO3).
There arises a problem in which sound localization (phase, balance) discords between the SRCs 2 for respective channels in the SRC 2 due to a difference in processing time delays according to the sample rate converter having the configuration in FIG. 1.
According to an embodiment of the present invention, the following methods (1), (2), and the like have generally been applied:
(1) A method that is conducted, when sampling frequency conversion is performed, using a memory unit which subsequently writes input data or data oversampling the input data, and sequentially read data written with a prescribed address difference from a write address, and using an interpolation processor which performs interpolation processing on the data read from the memory unit. In this method, the address difference between the write address and the read address of the memory unit is optimized. During a prescribed period of supplying input data, the difference between the addresses is optimized without any limitation, and after the prescribed period, the optimization is performed with a certain limitation (see Patent Reference 1).
(2) A method of setting a common parameter between the SRCs for sampling frequency conversion processing (hereinafter, referred to as “Matched-Phase mode processing” or “MP processing”) (see Non-patent Reference 1).
FIG. 3 is a diagram showing one configuration example of a sample rate converter using a Matched-Phase mode processing of the methods, and the elements identical to those in FIG. 1 are provided with the same reference numerals. In this sample rate converter, an SRC 4-1 (Phase-Master) is provided to the first channel, and an SRC 4-2 (Slave 1) and an SRC 4-3 (Slave 2) are respectively provided to the second channel and the third channel, in place of the respective SRCs 2-1, 2-2 and 2-3 shown in FIG. 1.
A TDM_IN terminal of the SRC 4-1 is grounded, and a code 3′b000 (setting code indicating Phase-Master) is supplied to an MMODE terminal of the SRC 4-1. Based on the code 3′b000, the SRC 4-1 performs sampling frequency conversion on the audio data S1 supplied from the AES input processing circuit 1-1 in synchronization with a phase detected from the audio data S1. The SRC 4-1 then multiplexes detected phase information (Matched-Phase data) with the audio data on which sampling frequency conversion is performed, and outputs the multiplexed data as shown in FIG. 4. In FIG. 3, the Matched-Phase data S6 is supplied to the TDM_IN terminals of the SRC 4-2 and SRC 4-3.
A code 3′b100 (setting code indicating Slave) is supplied to MMODE terminals of the SRC 4-2 and SRC 4-3. Based on the code 3′b100, the SRC 4-2 and SRC 4-3 respectively perform sampling frequency conversion on the audio data S1 supplied from the AES input processing circuits 1-2 and 1-3 in synchronization with the Matched-Phase data S6 which is inputted into the TDM_IN terminals.
Accordingly, the SRC 4-1, SRC 4-2 and SRC 4-3 respectively operate in synchronization with the common phase (phase detected by SRC 4-1).
[Patent Reference 1] Japanese Unexamined Patent Publication No. 2002-158619 (paragraphs 0049, 0067 to 0069, FIGS. 1, 2 and 6)
[Non-patent Reference 1] “192 kHz Stereo Asynchronous Sample Rate Converter AD1896” ANALOG DEVICES, retrieved from Nov. 7, 2005, Internet <URL:http://www.analog.com/UploadedFiles/Data_Sheets/71654447AD1 896_a.pdf>